A variety of semiconductor memory elements have been utilized to provide integrated circuit random access memories and read only memories. Dynamic memory cells and static memory cells have been utilized. Most of the semiconductor memory elements, however, have been volatile. That is, stored data is lost when a power shutdown or power failure occurs. MNOS transistors have been utilized to construct non-volatile memory elements. The operation of such non-volatile memory elements, however, has been such that relatively tight tolerances are required on one or both of the high and low threshold voltages which can be written into the composite dielectric structure of an MNOS transistor corresponding to a logical "1" or a logical "0". MNOS processing required to achieve the necessary tolerances is at the present time inadequate to provide the required tolerance at an economical cost and yet maintain acceptable reliability.